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DATA BULLETIN
MX429A
Features
Band III & General Purpose Trunked Radio Apps Full-Duplex 1200 and 2400 Baud Operation Error Check Word Generation and Checking Preamble Generation Processor Compatible Interface
CARRIER DETECT TIME CONSTANT RECEIVER INPUT DATA
1200/2400bps MSK Modem
for Trunked Radio Systems
Frame SYNC and SYNT Detection Low Power Consumption General Purpose Timer
RX MESSAGE FORMAT MSK RECEIVER
SYNC/SYNT DETECTOR
BYTE COUNTER
CHECKSUM CHECKER
RX CHECKSUM TRUE STATUS REGISTER SYNC SYNT RX DATA READY
1200/2400 BAUD MICROPROCESSOR INTERFACE STROBE RX CARRIER DETECT R/W A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 VBIAS VSS VDD XTAL/CLOCK XTAL CLOCK GENERATORS 1.008 MHz OUTPUT CLOCKS
RECOVERED CLOCK
DATA
RX DATA REGISTER 8-BIT uP BUS RX DATA BUFFER
RX CARRIER DET. RX CHECKSUM TRUE TX DATA READY TX IDLE
8-BIT uP BUS CONTROL REGISTER
RX ENABLE TX ENABLE RX MESSAGE FORMAT TX PARITY ENABLE
TX DATA BUFFER
TIMER EXPIRED
CHECKSUM GENERATOR
TX DATA REGISTER MSK TRANSMITTER BYTE COUNTER
TX PARITY ENABLE
TRANSMITTER OUTPUT
TIMER
RX DATA RDY TX DATA RDY SYNC SYNT TX IDLE
INTERRUPT IRQ GENERATOR
The MX429A is a single-chip CMOS 1200 and 2400 baud MSK modem, designed primarily for use in Trunked Radio Systems but may also be employed in other general purpose radio or line data communication applications. The device has been designed to conform to the UK Band III trunked radio protocols MPT 1317/1327. The MX429A is full duplex at 1200 and 2400 baud and includes an 8-bit parallel microprocessor interface and a programmable timer which may be set for interrupt periods of 8 to 120 bits. Preamble may be generated by the device in transmit. The 16-bit SYNC or SYNT words are detected in receive. An error check word is automatically generated in transmit and error checking is performed in the receive mode. An on-chip Xtal/clock generator requiring an external 4.032MHz Xtal or clock input provides both 4.032MHz and 1.008MHz outputs and performs all modem timings. The MX429A requires a single 5-volt power supply, has a powersave facility, and is available in the following package styles: 24-pin CDIP (MX429AJ), 24-pin PDIP (MX429AP), and 24-pin PLCC (MX429ALH).
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
2
MX429A
CONTENTS
Section Page
1 Block Diagram................................................................................................................. 3 2 Signal List........................................................................................................................ 3 3 External Components..................................................................................................... 5 4 General Description........................................................................................................ 6
4.1 Modems in Mobile Data Signaling .......................................................................................... 6
4.1.1 Digital Code Format.................................................................................................................... 6 4.1.2 Operation.................................................................................................................................... 6 4.1.3 Non MPT Application - Full-Duplex.......................................................................................... 7 4.1.4 Control Register (A1 = 1, A0 = 1, R/ W = 0, Write Only)........................................................... 7 4.1.5 Status Register (A1 = 1, A0 = 1, R/ W = 1, Read Only) ............................................................ 8 4.1.6 Rx Data Buffer (A1 = 1, A0 = 0, R/ W = 1, Read Only) ............................................................. 9 4.1.7 Tx Data Buffer (A1 = 1, A0 = 0, R/ W = 0, Write Only).............................................................. 9
4.2 Syndrome Word.................................................................................................................... 10
4.2.1 Syndrome Low Byte (A1 = 0, A0 = 0, R/ W = 1, Read Only) .................................................. 10 4.2.2 Syndrome High Byte (A1 = 0, A0 = 1, R/ W = 1, Read Only).................................................. 10
4.3 Carrier Detect Time Constant............................................................................................... 10
5 Application .................................................................................................................... 11
5.1 Checksum Generation and Checking................................................................................... 11 5.2 Receive Operation................................................................................................................ 11 5.3 Transmit Operation............................................................................................................... 12 5.4 Basic Power Up Software..................................................................................................... 13 5.5 Basic Software Interrupt Flow............................................................................................... 14 5.6 Bus Interface Timing............................................................................................................. 15
5.6.1 Bus interface design migration from MX429 to MX429A .......................................................... 15
6 Performance Specification........................................................................................... 15
6.1 Electrical Performance ......................................................................................................... 15
6.1.1 Absolute Maximum Ratings ...................................................................................................... 15 6.1.2 Operating Limits ....................................................................................................................... 15 6.1.3 Operating Characteristics ......................................................................................................... 16 6.1.4 Timing....................................................................................................................................... 18
6.2 Packaging............................................................................................................................. 18
MX*COM, Inc. reserves the right to change specifications at any time and without notice.
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
3
MX429A
1 Block Diagram
CARRIER DETECT TIME CONSTANT RECEIVER INPUT DATA RX MESSAGE FORMAT MSK RECEIVER
SYNC/SYNT DETECTOR
BYTE COUNTER
CHECKSUM CHECKER
RX CHECKSUM TRUE STATUS REGISTER SYNC SYNT RX DATA READY
1200/2400 BAUD MICROPROCESSOR INTERFACE STROBE RX CARRIER DATA DETECT R/W A1 A0 D7 D6 8-BIT uP BUS D5 D4 D3 D2 D1 D0 VBIAS VSS VDD XTAL/CLOCK XTAL CLOCK GENERATORS 1.008 MHz OUTPUT CLOCKS
RECOVERED CLOCK
RX DATA REGISTER 8-BIT uP BUS RX DATA BUFFER
RX CARRIER DET. RX CHECKSUM TRUE TX DATA READY TX IDLE TX DATA BUFFER TIMER EXPIRED
CONTROL REGISTER
RX ENABLE TX ENABLE RX MESSAGE FORMAT TX PARITY ENABLE
CHECKSUM GENERATOR
TX DATA REGISTER MSK TRANSMITTER BYTE COUNTER
TX PARITY ENABLE
TRANSMITTER OUTPUT
TIMER
RX DATA RDY TX DATA RDY SYNC SYNT TX IDLE
INTERRUPT IRQ GENERATOR
Figure 1: Block Diagram
2 Signal List
Pin No. J/P 1 2 LH 1 2 Signal Name VBIAS Transmit Output Output Type The internal circuitry bias line, held at VDD/2 this pin must be decoupled to VSS by a capacitor, see Figure 2. The 1200 baud, 1200Hz/1800Hz and 2400 baud, 1200Hz/2400Hz MSK Tx output. When not enabled by the Control Register (D0) its output impedance is set high. The 1200/2400 baud received MSK signal input. The 1200Hz/1800Hz, 1200Hz/2400Hz audio to this pin must be ac coupled via a capacitor, see Figure 2. Positive Supply. A single +5V regulated supply is required. It is recommended that this power rail be decoupled to VSS by a capacitor, see Figure 2. The on-chip Carrier Detect function requires external component(s) on this pin. See Figure 2for recommended component(s). The input to the clock oscillator inverter. A 4.032 MHz Xtal or externally derived clock pulse input should be connected here, see Figure 2. The output of the 4.032 MHz clock oscillator. Description
3
4
Receiver Input
Input
5
5
VDD
Power
6
6
Carrier Detect Time Constant: Xtal/Clock
7
7
8
8
XTAL
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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1200/2400bps MSK Modem for Trunked Radio Systems
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MX429A
Pin No. J/P 9 10 11 12 13 14 15 16 17 18 19 LH 9 10 11 12 13 14 15 16 17 18 19 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1
Signal Name Type
Description
Microprocessor Data Interface These 8 lines are used by the device to communicate with a microprocessor with the R/ W , A0 and A1 inputs determining register selection.
Register Selection: These inputs, with the R/ W input, select the required register to the data bus as shown in Table 2 Performs the dual functions of selecting the device for Read or Write and strobing data in or out. It should be generated by gating the high order address bits with a Read/Write clock. The MX429A is selected when this pin is a logic `0'. Used in conjunction with A1 and A0 to determine which internal registers are connected to the data interface pins (D0 to D7) during Strobe. Interrupt Request. This line will go to a logic '0' when an interrupt occurs. This output can be "wire OR'd" with other active low components (100kW pullup to VDD). The conditions that cause the interrupts are indicated at the Status Register and are as follows: Timer Expired, Rx Data Ready, Tx Data Ready, Tx Idle, Rx SYNC Detect, Rx SYNT Detect A logic `1' on this pin selects the 1200 baud option. Tone frequencies are: one cycle of 1200Hz represents a logic `1', one and a half cycles of 1800Hz represents a logic `0'. A logic `0' on this pin selects the 2400 baud option. Tone frequencies are: one half cycle of 1200Hz represents a logic `1', one cycle of 2400Hz represents a logic `0'. This pin has an internal 1M pullup resistor. Power Negative Supply (GND) A 1.008 MHz (X1 / 4) clock is available at this output for external circuit use, note the source impedance and source current limits. Leave this pin open-circuit Table 1: Signal List Register Control Status Rx Data Tx Data Syndrome Low Syndrome High R/ W 0 1 1 0 1 1 A0 1 1 0 0 0 1 A1 1 1 1 1 0 0
STROBE
20
20
R/ W
21
21
IRQ
22
24
1200 / 2400 Baud Select
23 24 4
22 23 3
VSS Clock/4
Table 2: Register Selection
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
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Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
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MX429A
3 External Components
VDD
VBIAS TRANSMIT OUTPUT RECEIVE INPUT C3 VDD
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
CLOCK/4 VSS 1200/2400 BAUD SELECT IRQ R/W STROBE A1 A0 D7 D6 D5 D4
C4 C5 R2 C6
'CD' TIME CONSTANT XTAL/CLOCK XTAL D0 D1 D2 D3
Recommended Xtal Component Xtal/Clock X1 R1 8 XTAL 7 MX429A
C1 C2
D0 D1 D2 D3 D4 D5 D6 D7 MICROPROCESSOR DATA INTERFACE
Figure 2: Recommended External Components
R1 R2 C1 C2 C3
1M 1M 33pF 33pF 0.1F
10% 10% 20% 20% 20%
C4 C5 C6 X1 Note 1
1.0F 1.0F 1.0F 4.032MHz
20% 20% 20%
Table 3: Recommended External Components
Notes: 1. For best results, a crystal oscillator design should drive the clock inverter input with signal levels of at least 40% of VDD, peak to peak. Tuning fork crystals generally cannot meet this requirement. To obtain crystal oscillator design assistance, consult your crystal manufacturer.
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
6
MX429A
4 General Description
4.1
4.1.1
Modems in Mobile Data Signaling
Digital Code Format
The MPT 1327 Signaling Standard for Trunked LMR Systems protocol is used by the MX429 for communication between a Trunking System Controller (TSC) and users' radio units. These data stream formats are summarized in Figure 3.
Preamble For bit sync. 101010...10..- bit reversals Minimum 16 bits, ending in logic'0' SYNC or SYNT SYNC Word 1100010011010111 SYNT Word 0011101100101000 Address Code Word 64 Bits Optional Data Code Words
Address Code Word Structure Bit No. No. of Bits Bit Name 1 1 Logic '1' 2 to 7 User Identity 8 9 to 40 Address & Data 48
(Bit number 1 is transmitted first) 49 to 16 Check Bits (Checksum) 64
Figure 3: Tx and Rx Data Stream
4.1.2
Operation
The MX429A can be used for Full-Duplex operation with the host microprocessor only having to operate on the data while the modem (MX429A) handles all other signaling routines and requirements. In the Tx mode the MX429A will : 1. Internally generate and transmit a preamble - bit reversals, for system bit synchronization. 2. Accept from the host, and transmit, a 16-bit 'SYNC' or 'SYNT' word. 3. Accept from the host, and transmit, 6 bytes of data (Address Code Word): A. Upon a software command, internally calculate and transmit a 2-byte checksum based on the previous 6 data bytes. B. Upon a software command, disable internal checksum generation and allow continuous data transmission. 4. Transmit 1 'hang bit' and go idle when all loaded data traffic has been sent (followed by a "Tx Idle" interrupt). In the Rx mode the MX429A will: 1. Detect and achieve bit synchronization within 16 bits. 2. Search for and detect the 16-bit 'SYNC'/'SYNT' word. 3. Output all received data after 'SYNC/SYNT,' in byte form. 4. Upon a software command (Rx Message Format), use the received checksum to calculate the presence (if any) of errors, and advise the host with an interrupt and a 16-bit Syndrome word. Note: In Rx, a software command is used to determine whether a 'SYNC'/'SYNT' word is required after every 8 (6 data + 2 checksum ) received bytes, or "data" is received continually. Normally the 'SYNC' word is used on the Control data channel and the 'SYNT' word is used on the Traffic data channel.
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
7
MX429A
4.1.3
Non MPT Application - Full-Duplex
The functions described in this section, to allow the MX429A modem to operate as a general purpose device, are obtained using the commands and indications detailed in the "Register Instructions" pages. Tx: When enabled the device transmits a "101010......10" preamble until data for transmission is loaded by the host microprocessor. Transmits 6 bytes of the loaded data followed by a 2-byte checksum based on that data. As long as Tx data is loaded the transmitter will transmit, the 2-byte checksum being produced after every 6 bytes (8 byte packages). Automatic checksum generation can be inhibited by a software command to allow transmission of continuous data streams. Rx: When enabled requires the 16-bit SYNC or SYNT word (see notes) before outputting data bytes. The modem receiver will then output continuous bytes of data, after every 6 bytes received a 2-byte checksum word will be output and can be ignored or used for error checking. 4.1.4 Control Register (A1 = 1, A0 = 1, R/ W = 0, Write Only)
The Control Register, when selected, directs the modem's operation as described in Table 4
Bit Bit 0 D0 Description TX Enable Function Set: D0 enables the transmitter for operation. A '0 - 1' transition causes bit synchronization and the start of 1010.........10 preamble pattern transmission. At least one byte of preamble will be transmitted. If data is loaded into the Tx Data Buffer before one byte has been sent then that data will follow, otherwise whole bytes of preamble will continue until data is loaded. Clear: The Transmitter Output pin is set to a high impedance and no transmitter interrupts are produced. Set: D1 indicates to the transmitter that 2-byte checksums are to be generated by the modem. A '0 - 1' transition starts checksum generation on the next six bytes loaded from the Tx Data Buffer into the Tx Data Register. Checksum generation continues for every 6 bytes loaded until this bit is cleared. The transmitter will send the generated checksum (2 bytes) after the last of each 6 bytes have been sent. If an underrun (no more data loaded) condition occurs before 6 bytes have been loaded checksum generation will abort, the transmission will cease after one 'hang' bit has been sent and Bit 4 in the Status Register (Tx Idle) will be set. No checksum will be transmitted. Clear: No checksum generation is carried out and the host may supply the checksum bytes. The output is then "as written". Set: D2 enables the receiver for operation. No data is produced (i.e. No Rx Data Ready interrupts) until a 'SYNC' or 'SYNT' word is found in the received bit stream. Clear: The receiver is disabled and all interrupts caused by the receiver are inhibited. Set: D3 is sampled after a checksum has been received and allows the host to control the way the receiver handles the following data bits. If 'set' the receiver will assume that the next 6 bytes are data and will start error checking accordingly. Clear: The receiver will stop data transfer to the host after the 2 checksum bytes until another 'SYNC' or 'SYNT' frame word is received.
Bit 1 D1
Tx Parity Enable
Bit 2 D2 Bit 3 D3
Rx Enable
Rx Message Format
Bit 4 D4 Bit 5 D5 Bit 6 D6 Bit 7 D7
Timer LSB Timer Timer Timer MSB If a new timer value is written to these inputs within 1 byte period of the last timer interrupt then the next timer period will be correct without first having to reset the timer, otherwise the timer must be reset to zero and then set to the new time. If using the internal Tx preamble generation facility, e.g. with the internal timer setting the preamble length, the device may occasionally produce a Tx Ready interrupt immediately after a Tx Enable command. User software should handle this occurrence by either: a. Detecting that the timer interrupt status bit is not set and that it is not appropriate to load Tx data at this time. b. Not using the timer. i.e. immediately after Tx Enable, reading the Status Register and loading a byte of preamble. This resets any interrupt. The length of preamble transmitted is now controlled by the number of bytes loaded. Reference Table 5
Tx Enable
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
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MX429A
Table 4: Control Register D7 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Reset counter and disable timer interrupts Count and interrupt every " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " " 8 16 24 32 40 48 56 64 72 80 88 96 104 112 120 bits bits bits bits bits bits bits bits bits bits bits bits bits bits bits
Table 5: Timer Control Bits
4.1.5
Status Register (A1 = 1, A0 = 1, R/ W = 1, Read Only)
When an interrupt is generated, the IRQ Output goes low with the Status Register bits indicating the sources of the interrupt.
Bit Bit 0 D0 Description Rx Data Ready Function D0: when set, causes an interrupt indicating that received data is ready to be read from the Rx Data Buffer. This data must be read within 8 bit periods. Set when a byte of data is loaded into the Rx Data Buffer, if a frame (SYNC/SYNT) word has been received. Bit and Interrupt Cleared: (i). by a read of the Status Register followed by a read of the Rx Data Buffer (ii). by Rx Enable going Low. D1: when set, indicates that the error checking on the previous 6 bytes agreed with the received checksum. This function, which is valid when the Rx Data Ready bit (D0) is set for the second byte of the received checksum, does not cause an interrupt. Set: by a correct comparison between the received and generated checksums. Cleared: (i). by a read of the Status Register followed by a read of the Rx Data Buffer (ii). by Rx Enable going Low. D2: is a "Real Time" indication from the modem receiver's carrier detect circuit and does not cause an interrupt. When MSK tones are present at the receiver input this bit goes High, for no MSK input this bit goes Low. When the Rx Enable bit (D2- Control Register) is Low Rx Carrier Detect will go Low. D3: when set, causes an interrupt to indicate that a byte of data should be written to the Tx Data Buffer within 8 bit periods. Set: (i). when the contents of the Tx Data Buffer are transferred to the Tx Data Register (ii). when the Tx Enable is set (No interrupt is generated in this case. Bit Cleared: (i). by a read of the Status Register followed by a write to the Tx Data Buffer (ii). by Tx Enable going Low. Interrupt Cleared:
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Bit 1 D1
Rx Checksum True
Bit 2 D2
Rx Carrier Detect
Bit 3 D3
Tx Data Ready
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1200/2400bps MSK Modem for Trunked Radio Systems
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MX429A
Bit
Description
Function (i). by a read of the Status Register (ii). by Tx Enable going Low. D4: causes an interrupt when set, to indicate that all loaded data and one 'hang' bit have been transmitted. Set: one bit period after the last byte is transmitted. This last byte could be either "checksum" or " loaded data" depending upon the Tx Parity Enable state (Control Register D1). Bit Cleared: (i). by a write to the Tx Data Buffer (ii). by Tx Enable going Low. Interrupt Cleared: (i). by a read of the Status Register (ii). by Tx Enable going Low. D4: causes an interrupt when set, to indicate that all loaded data and one 'hang' bit have been transmitted. Set: one bit period after the last byte is transmitted. This last byte could be either "checksum" or " loaded data" depending upon the Tx Parity Enable state (Control Register D1). Bit Cleared: (i). by a write to the Tx Data Buffer (ii). by Tx Enable going Low Interrupt Cleared: (i). by a read of the Status Register (ii). by Tx Enable going Low. D6: when set, causes an interrupt to indicate that a 16-bit 'SYNC' word (1100010011010111) has been detected in the received bit stream. Set: on receipt of the 16th bit of a 'SYNC' word. Bit and Interrupt Cleared: (i). by a read of the Status Register (ii). by Rx Enable going Low. D7: when set, causes an interrupt to indicate that a 16-bit 'SYNT' word (0011101100101000 ) has been detected in the received bit stream. Set: on receipt of the 16th bit of a 'SYNT' word. Bit and Interrupt Cleared: (i). by a read of the Status Register (ii). by Rx Enable going Low.
Bit 4 D4
Tx Idle
Bit 5 D5
Timer Interrupt
Bit 6 D6
Rx SYNC Detect *
Bit 7 D7
Rx SYNT Detect *
* SYNC and SYNT Detection is disabled while the checksum checker is running.
Table 6: Status Register
4.1.6
Rx Data Buffer (A1 = 1, A0 = 0, R/ W = 1, Read Only)
These 8 bits are the last byte of data received with bit 7 being received first. Note the relative positions of the MSB and LSB presented in this bit stream, the position may be different to the convention used in other Processor peripherals. D0 LSB 4.1.7 D1 D2 D3 D4 D5 D6 D7 MSB
Tx Data Buffer (A1 = 1, A0 = 0, R/ W = 0, Write Only)
These 8 bits loaded to the Tx Data Buffer are the next byte of data that will be transmitted, with bit 7 being transmitted first. Note the relative positions of the MSB and LSB presented in this bit stream, the position may be different to the convention used in other Processor peripherals. If the Tx Parity Enable bit (Control Register D1 ) is set, a 2-byte checksum will be inserted and transmitted by the modem after every 6 transmitted "message" bytes. D0 LSB D1 D2 D3 D4 D5 D6 D7 MSB
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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Fax: 336 744-5054
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1200/2400bps MSK Modem for Trunked Radio Systems
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MX429A
4.2
Syndrome Word
This 16-bit word (both Low and High bytes) may be used to correct errors. Bits S1 to S15 are the 15 bits remaining in the polynomial divider of the checksum checker at the end of 6 bytes of " received message." For a correct message all 15 bits (S1 to S15) will be zero. The 2 Syndrome bytes are valid when the Rx Data Ready bit (Status Register D0) is set for the second byte of the received checksum and should be read, if required, before 8 byte periods. 4.2.1 Syndrome Low Byte (A1 = 0, A0 = 0, R/ W = 1, Read Only) D0 S1 4.2.2 D1 S2 D2 S3 D3 S4 D4 S5 D5 S6 D6 S7 D7 S8
Syndrome High Byte (A1 = 0, A0 = 1, R/ W = 1, Read Only) D0 S9 D1 S10 D2 S11 D3 S12 D4 S13 D5 S14 D6 S15 D7 Parity Error
D7: This is a "Parity Error Bit". Indicating an error between the received parity bit and the parity bit internally generated from the incoming message. Therefore a correctly received message all 16 bits of the Syndrome Word (S1 to S15 and Parity Error) will be zero.
4.3
Carrier Detect Time Constant
The value of the Carrier Detect capacitor, C5, determines the carrier detect time constant. A long time constant (larger value C5) results in improved noise immunity but increased response time. C5 may be varied to optimize noise immunity/response time. 1. With R2 = 1M and C5 = 1F as external components for the carrier detect function at 1200 baud only. 2. By using C5 = 0.1F and removing R2 completely the MX429A will operate at both 1200 and 2400 baud rates.
2 x 10-2 10-2
Ideal Coherent MSK Characteristic MX429A Characteristic
Bit Error Rate (Logarithmic Scale)
10-3
10-4 8 6 4 3 2 10-5 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Signal to Noise Ratio (dB) [Bit-Rate Bandwidth] (Linear Scale)
Figure 4: Bit Error Rate vs. Signal to Noise Ratio
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
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Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
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MX429A
5 Application
5.1 Checksum Generation and Checking
Generation - The checksum generator takes the 48 bits from the 6 bytes loaded into the Tx Data Buffer and divides them modulo-2, by the generating polynomial;X15 + X14 + X13 + X11 + X4 + X2 + 1 It then takes the 15-bit remainder from the polynomial divider, inverts the last bit and appends an EVEN parity bit generated from the initial 48 bits and the 15 bit remainder (with the last bit inverted). This 16-bit word is used as the "Checksum." Checking - The checksum checker does two things: It takes the first 63 bits of a received message, inverts bit 63, and divides them modulo-2, by the generating polynomial;X15 + X14 + X13 + X11 + X4 + X2 + 1 The 15 bits remaining in the polynomial divider are checked for all zero. Secondly, it generates an EVEN parity bit from the first 63 bits of a received message and compares this bit with the received parity bit (bit 64). If the 15 bits in the polynomial divider are all zero, and the two parity bits are equal, then the Rx Checksum True bit (SR D1) bit is set.
5.2
Receive Operation
MODE 1
Rx ENABLE
Where SYNC/SYNT is required after every message
Rx INPUT
SYNC
SYNC
A1
A2
A3
A4
A5
A6
C1
C2
SYNC
SYNC
A1
A2
A3
A4
A5
A6
C1
C2
SYNC
IRQ OUTPUT READ STATUS REGISTER
Rx DATA READY
SYNC (SYNT) DETECT Rx CHECKSUM TRUE
READ Rx DATA BUFFER A1 Rx MESSAGE FORMAT A2 A3 A4 A5 A6 C1 C2 A1 A2 A3 A4 A5 A6 C1 C2
MODE 2
Rx INPUT SYNC
Where additional data will follow the initial address data, indicated by the state of the Rx Message Format bit
{additional Data Words} SYNC A1 A2 A3 A4 A5 A6 C1 C2 D1 D2 D3 D4 D5 D6 C1 C2 D1
IRQ OUTPUT
READ STATUS REGISTER
Rx DATA READY
SYNC (SYNT) DETECT Rx CHECKSUM TRUE
READ Rx DATA BUFFER A1 Rx MESSAGE FORMAT A2 A3 A4 A5 A6 C1 C2 D1 D2 D2 D4 D5 D6 C1 C2
Rx Message Format is sampled at this point to decide, (a) whether the message is complete or (b), more data follows Note: A - Address, C - Checksum, D - Datacode
Figure 5: Receive Operation
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
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Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
12
MX429A
5.3
Transmit Operation
(a) Tx - one message with checksum supplied by host
Tx ENABLE (2) (1) (2)
Tx INPUT
P1
P2
Pn
S1
S2
A1
A2
A3
A4
A5
A6
C1
C2
H (3)
IRQ OUTPUT Tx DATA READY WRITE TO Tx DATA BUFFER READ STATUS REGISTER Tx PARITY ENABLE
S1
S2
A1
A2
A3
A4
A5
A6
C1
C2
Tx IDLE
(b) Tx - one message with checksum generated internally
Tx ENABLE (2) (1) (2)
Tx INPUT
P1
P2
Pn
S1
S2
A1
A2
A3
A4
A5
A6
C1
C2
H (3)
IRQ OUTPUT Tx DATA READY WRITE TO Tx DATA BUFFER READ STATUS REGISTER Tx PARITY ENABLE
S1
S2
A1
A2
A3
A4
A5
A6
Tx IDLE
(c) Tx - more than one message, with checksum generated internally
Tx ENABLE (2) P1 P2 Pn S1 S2 A1 A2 A3 A4 A5 A6 C1 C2 S1 S2 A1 A2 A3 A4 A5 A6 C1 C2 S1
Tx INPUT
IRQ OUTPUT Tx DATA READY WRITE TO Tx DATA BUFFER READ STATUS REGISTER Tx PARITY ENABLE
S1
S2
A1
A2
A3
A4
A5
A6
S1
S2
A1
A2
A3
A4
A5
A6
S1
Tx Parity Enable is 'Low' - indicating that the SYNC/SYNT word is not to be included in the next checksum
A6 C1 C2 D1 D2 D3 D4 D5 D6 C1 C2 H Tx INPUT
Notes: A C D H P S (1) (2) (3) Address Code Checksum Data Code Hang Bit Preamble SYNC/SYNT Tx Output at bias level Tx Output at High Impedance If Tx Data Ready is Set here, it inhibits Tx Data Ready Interrupt - The Tx Idle Interrupt occurs 1 bit later
IRQ OUTPUT Tx DATA READY WRITE TO Tx DATA BUFFER READ STATUS REGISTER Tx PARITY ENABLE
D1
D2
D3
D4
D5
D6
Tx Parity Enable remains 'High' - indicating that all following data is to be included in the checksum
Tx IDLE
Figure 6: Transmit Operation
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
13
MX429A
5.4
Basic Power Up Software
Power Up
Set up a 1 byte variable - initialise to zero (Rx Msg Length)
Set up an 8 byte buffer start address - (Rx Buffer)
Set up a 1 byte variable - initialise to zero (Tx Msg Sent)
Set up an 8 byte variable start address - (Tx Buffer)
Write 04 to Control Register
- Wait at least 1 bit -
Write zeros to MX 429A Control Register
Enable microprocessor interrupts
Transmit
Receive or Transmit?
Receive
Put message for transmission into buffer [Tx Buffer]
Write to Control Register Bit0 - Tx Enable = '1' Bit1 - Tx Parity Enable = '0'
Write to Control Register Bit2 - Rx Enable = '1' Bit3 - Rx Message Format = '0'
Wait 1 byte (Specification requires a minimum of two bytes preamble)
Write [Tx Buffer{O}] to Tx Data Buffer
Return to Main Program
Figure 7: Basic Power-Up Software
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
14
MX429A
5.5
Basic Software Interrupt Flow
Figure 8: Basic Software Interrupt Flow
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
15
MX429A
5.6
Bus Interface Timing
It is very important that circuit designs conform to the bus interface timing specification as described in Section 6.1.4. Failure to do so can result in intermittent operation that is difficult to troubleshoot. For example, if the bus timing is incorrect, the required two step READ Rx data transaction (1: Read Status Register, 2: Read Rx Data Buffer) may fail on step 2. As a result, the MX429A IRQ will not be reset and subsequently expected IRQ's will not occur. This symptom might be incorrectly interpreted as an MX429A functional failure but is, in fact, caused by the circuit design's bus interface timing violation. Other examples can occur on WRITE transactions that fail to properly clear the IRQ and so prevent subsequently expected IRQ's from occurring. Circuit designs should be careful to strictly conform to the tDHW specification, the Data Hold Time (Write), as assumed requirements may be incorrect. 5.6.1 Bus interface design migration from MX429 to MX429A
The MX429A bus interface timing requirements precisely match those of its predecessor, the MX429. As a result, properly designed and operated MX429 bus interface circuits are compatible with the MX429A device. It should be noted that the MX429 and MX429A device may behave differently in those designs, which violate the bus timing specification. However, this is caused by the timing violation rather than an incompatibility between the two devices.
6 Performance Specification
6.1
6.1.1
Electrical Performance
Absolute Maximum Ratings
Exceeding these maximum ratings can result in damage to the device. General Supply (VDD-VSS) Voltage on any pin to VSS Current VDD VSS Any other pin J / P / LH Package Total allowable Power Dissipation at TAMB = 25C Derating above 25C Operating Temperature Storage Temperature 6.1.2 Operating Limits -40 -55 10 85 125 800 mW mW/C above C C C -30 -30 -20 30 30 20 mA mA mA Notes Min. -0.3 -0.3 Typ. Max. 7.0 VDD + 0.3 Units V V
Correct operation of the device outside these limits is not implied. Notes Supply (VDD-VSS) Operating Temperature Xtal Frequency Min. 4.5 -40 4.032 Typ. 5.0 Max. 5.5 85 Units V C MHz
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
16
MX429A
6.1.3
Operating Characteristics
For the following conditions unless otherwise specified: VDD = 5.0V, TAMB = 25C, Xtal/Clock f0 = 4.032MHz Bit Rate Bandwidth = 1200Hz, Audio Level 0dB ref: = 300mVRMS Static Values Supply Current Ranges Rx and Tx Enabled Rx Enabled, Tx Disabled Rx Disabled, Tx Enabled Rx and Tx Disabled Dynamic Values Modem Internal Delay Interface Levels Output Logic '1' Source Current Output Logic '0' Sink Current Three State Output Leakage Current D0 - D7 Data In/Out Logic '1' Level Logic '0' Level A1, A0, R/W, STROBE, IRQ Logic '1' Level Logic '0' Level Analog Impedance's Rx Input Tx Output (Enabled) Tx Output (Disabled) On-Chip Xtal Oscillator RIN ROUT Oscillator Gain Xtal frequency Receiver Signal Input Levels Bit Error Rate @ 12dB Signal/Noise Ratio @ 20dB Signal/Noise Ratio Synchronization @ 12dB Signal/Noise Ratio Probability of Bit 16 being correct Carrier Detect Response Time 8 8 99.5 13.0 % ms 6 7 7.0 1.0 10-4 10-8 -9.0 -2.0 10.5 dB 5 10.0 30.0 25.0 4.032 M k dB MHz 100 10 5.0 k k M 4 4.0 1.0 V V 1 3.5 1.5 V V 2 3 120 360 4.0 A A A 1.5 ms 1.5 4.0 7.0 6.0 7.0 2.5 mA mA mA mA Notes Min. Typ. Max. Units
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
17
MX429A
Static Values Transmitter Output Level Output Level Variation Output Distortion 3rd Harmonic Distortion Logic '1' Frequency Logic '0' Frequency Isochronous Distortion 1200Hz - 1800Hz/1200Hz - 2400Hz 1800Hz - 1200Hz/2400Hz - 1200Hz Operating Characteristics Notes: 1. With each data line loaded as, C = 50pf and R = 10k. 2. VOUT = 4.6V. 3. VOUT = 0.4V 4. Sink/Source currents 0.1mA. 5. Both Xtal and Xtal 4 Outputs. 6. With 50dB Signal/Noise Ratio. 7. See Figure 4, Bit Error Rate. 1200 baud 2400 baud 1200 baud 2400 baud
Notes
Min.
Typ. 8.25
Max.
Units dB
10
-1.0 3.0 2.0
1.0 5.0 3.0
dB % % Hz Hz Hz Hz
9 9 9 9 25 20
1200 1200 1800 2400 40 40 s s
8. This Response Time is measured using a 10101010101.... 01 pattern input signal at a level of 230mVRMS (-2.3dB) with no noise. 9. Dependent upon Xtal tolerance. 10. The amplitude difference between the Transmit Output signals (tones) representing a logic `0' a logic `1'.
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
18
MX429A
6.1.4
Timing
Timing see Figure 9 (tACS) (tAH) (tAS) (tDHW) (tDS) (tOHR) (tST) Access Time Address Hold Time Address Set-up Time Data Hold Time (Write) Data Set-up Time (Write) Output Hold Time (Read) Strobe Time 0 0 85 0 15 140 105 Min. Typ. Max. 135 Units ns ns ns ns ns ns ns
A0
A1
A2 tAS tAH tOHR tST
STROBE
DATA OUT (READ) VALID DATA tDS DATA IN (WRITE) VALID DATA
tACS - Access Time tAS - Address Set-Up Time tDS - Data Set-Up Time tAH tDHW tOHR tST Address Hold Time Data Hold Time (Write) Output Hold Time (Read) Strobe Time
tACS
tDHW
Figure 9: Timing Diagram
6.2
Packaging
A
Package Tolerances
DIM. MIN. TYP. MAX. A B C E E1 F H J J1 K K1 L P T
1.260 (32.00) 1.240 (31.50) 0.583 (14.79) 0.514 (13.06) 0.165 (4.19) 0.230 (5.84) 0.600 (15.23) 0.670 (17.00) 0.594 (15.09) 0.615 (15.61) 1.100 (27.94) 0.02 (0.51) 0.018 (0.46) 0.055 (1.39) 0.050 (1.27) 0.080 (2.03) 0.074 (1.88) 0.080 (2.03) 0.115 (2.92) 0.200 (5.08) 0.10 (2.54) 0.0106 (0.269) 0.0094 (0.239)
B
E1
E
PIN1 K H L J J1 F P K1 C
T
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 10: 24-pin CDIP Mechanical Outline: order as part no. MX429AJ
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
1200/2400bps MSK Modem for Trunked Radio Systems
19
MX429A
A
Package Tolerances
DIM. A B C E E1 H J J1 K L P T Y MIN. TYP. MAX.
1.270 (32.26) 1.200 (30.48) 0.555 (14.04) 0.500 (12.70) 0.151 (3.84) 0.220 (5.59) 0.600 (15.24) 0.670 (17.02) 0.590 (14.99) 0.625 (15.88) 0.015 (0.38) 0.045 (1.14) 0.015 (0.38) 0.023 (0.58) 0.040 (1.02) 0.065 (1.65) 0.066 (1.67) 0.074 (1.88) 0.121 (3.07) 0.160 (4.05) 0.100 (2.54) 0.008 (0.20) 0.015 (0.38) 7 NOTE : All dimensions in inches (mm.) Angles are in degrees
B
E1
Y
E
PIN1
T
K H L J J1 P
C
Figure 11: 24-pin PDIP Mechanical Outline: order as part no. MX429AP
E B Y DA
W
C K J W T H
Package Tolerances
DIM. A B C D E F G H J K P T W Y MIN. TYP. MAX.
0.409 (10.40) 0.380 (9.61) 0.409 (10.40) 0.380 (9.61) 0.146 (3.70) 0.128 (3.25) 0.417 (10.60) 0.435 (11.05) 0.435 (11.05) 0.417 (10.60) 0.250 (6.35) 0.250 (6.35) 0.023 (0.58) 0.018 (0.45) 0.022 (0.55) 0.047 (1.19) 0.048 (1.22) 0.051 (1.30) 0.049 (1.24) 0.009 (0.22) 0.006 (0.152) 30 45 6
PIN 1 P
G F
NOTE : All dimensions in inches (mm.) Angles are in degrees
Figure 12: 24-pin PLCC Mechanical Outline: order as part no. MX429ALH
(c) 1998 MX-COM Inc.
4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA
www.mxcom.com Tel: 800 638-5577 336 744-5050
All trademarks and service marks are held by their respective companies.
Fax: 336 744-5054
Doc. # 20480128.007
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
CML Product Data
In the process of creating a more global image, the three standard product semiconductor companies of CML Microsystems Plc (Consumer Microcircuits Limited (UK), MX-COM, Inc (USA) and CML Microcircuits (Singapore) Pte Ltd) have undergone name changes and, whilst maintaining their separate new names (CML Microcircuits (UK) Ltd, CML Microcircuits (USA) Inc and CML Microcircuits (Singapore) Pte Ltd), now operate under the single title CML Microcircuits. These companies are all 100% owned operating companies of the CML Microsystems Plc Group and these changes are purely changes of name and do not change any underlying legal entities and hence will have no effect on any agreements or contacts currently in force. CML Microcircuits Product Prefix Codes Until the latter part of 1996, the differentiator between products manufactured and sold from MXCOM, Inc. and Consumer Microcircuits Limited were denoted by the prefixes MX and FX respectively. These products use the same silicon etc. and today still carry the same prefixes. In the latter part of 1996, both companies adopted the common prefix: CMX. This notification is relevant product information to which it is attached. CML Microcircuits (USA) [formerly MX-COM, Inc.] Product Textual Marking On CML Microcircuits (USA) products, the `MX-COM' textual logo is being replaced by a `CML' textual logo.
Company contact information is as below:
CML Microcircuits (UK)Ltd
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (USA) Inc.
COMMUNICATION SEMICONDUCTORS
CML Microcircuits (Singapore)PteLtd
COMMUNICATION SEMICONDUCTORS
Oval Park, Langford, Maldon, Essex, CM9 6WG, England Tel: +44 (0)1621 875500 Fax: +44 (0)1621 875600 uk.sales@cmlmicro.com www.cmlmicro.com
4800 Bethania Station Road, Winston-Salem, NC 27105, USA Tel: +1 336 744 5050, 0800 638 5577 Fax: +1 336 744 5054 us.sales@cmlmicro.com www.cmlmicro.com
No 2 Kallang Pudding Road, 09-05/ 06 Mactech Industrial Building, Singapore 349307 Tel: +65 7450426 Fax: +65 7452917 sg.sales@cmlmicro.com www.cmlmicro.com
D/CML (D)/2 May 2002

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